[IA64] Fix ld.s emulation

With this patch,
* XEN correctly emulates ld.s for HVM
* original memory attribute is preserved in vcpu->arch.vtlb

Without this, XEN infrequently calls panic_domain() by mistake for windows.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
Signed-off-by: Akio Takebe <takebe_akio@jp.fujitsu.com>

diff --git a/xen/arch/ia64/vmx/vmx_process.c b/xen/arch/ia64/vmx/vmx_process.c
index 0fb176af0d037aaea7a97eed47a7dd84dc93a905..f9035122507752f4bc9e78425c360015ef5f1a89 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_process.c
+++ b/xen/arch/ia64/vmx/vmx_process.c
@@ -311,6 +311,8 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
 
     if(is_physical_mode(v)&&(!(vadr<<1>>62))){
         if(vec==2){
+            if (misr.sp) /* Refer to SDM Vol2 Table 4-11,4-12 */
+                return vmx_handle_lds(regs);
             if (v->domain != dom0
                 && __gpfn_is_io(v->domain, (vadr << 1) >> (PAGE_SHIFT + 1))) {
                 emulate_io_inst(v,((vadr<<1)>>1),4);   //  UC
@@ -324,9 +326,16 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
 try_again:
     if((data=vtlb_lookup(v, vadr,type))!=0){
         if (v->domain != dom0 && type == DSIDE_TLB) {
+            if (misr.sp) { /* Refer to SDM Vol2 Table 4-10,4-12 */
+                if ((data->ma == VA_MATTR_UC) || (data->ma == VA_MATTR_UCE))
+                    return vmx_handle_lds(regs);
+            }
             gppa = (vadr & ((1UL << data->ps) - 1)) +
                    (data->ppn >> (data->ps - 12) << data->ps);
             if (__gpfn_is_io(v->domain, gppa >> PAGE_SHIFT)) {
+                if (misr.sp)
+                    panic_domain(NULL, "ld.s on I/O page not with UC attr."
+                                 " pte=0x%lx\n", data->page_flags);
                 if (data->pl >= ((regs->cr_ipsr >> IA64_PSR_CPL0_BIT) & 3))
                     emulate_io_inst(v, gppa, data->ma);
                 else {

diff --git a/xen/arch/ia64/vmx/vtlb.c b/xen/arch/ia64/vmx/vtlb.c
index 62862cb0c5c081d38c4a61c8b4ec5c210db3296e..8fa6b4c598291ac1dbaabfe3a5c31aeed1b68b84 100644 (file)
--- a/xen/arch/ia64/vmx/vtlb.c
+++ b/xen/arch/ia64/vmx/vtlb.c
@@ -507,6 +507,13 @@ u64 translate_phy_pte(VCPU *v, u64 *pte, u64 itir, u64 va)
         *pte |= VTLB_PTE_IO;
         return -1;
     }
+    /* Ensure WB attribute if pte is related to a normal mem page,
+     * which is required by vga acceleration since qemu maps shared
+     * vram buffer with WB.
+     */
+    if (phy_pte.ma != VA_MATTR_NATPAGE)
+        phy_pte.ma = VA_MATTR_WB;
+
 //    rr.rrval = ia64_get_rr(va);
 //    ps = rr.ps;
     maddr = ((maddr & _PAGE_PPN_MASK) & PAGE_MASK) | (paddr & ~PAGE_MASK);
@@ -530,17 +537,8 @@ int thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa, int type)
     vcpu_get_rr(current, ifa, &vrr.rrval);
     mrr.rrval = ia64_get_rr(ifa);
     if(VMX_DOMAIN(v)){
-        
         phy_pte = translate_phy_pte(v, &pte, itir, ifa);
 
-        /* Ensure WB attribute if pte is related to a normal mem page,
-         * which is required by vga acceleration since qemu maps shared
-         * vram buffer with WB.
-         */
-        if (!(pte & VTLB_PTE_IO) && ((pte & _PAGE_MA_MASK) != _PAGE_MA_NAT)) {
-            pte &= ~_PAGE_MA_MASK;
-            phy_pte &= ~_PAGE_MA_MASK;
-        }
         if (pte & VTLB_PTE_IO)
             ret = 1;
         vtlb_purge(v, ifa, ps);